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Vector Reduction can be done with AND_REDUCE/OR_REDUCE etc. It's in the std_logic_misc lib, and reduces everything down to a single bit.
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Gate assignment version of a combinatorial logic circuit.
-- Entity
entity gates is port (
vA, vB : in std_logic_vector(3 downto 0);
A,B,C,D : in std_logic;
W,U,X,Y,Z : out std_logic;
vX, vY : out std_logic_vector(3 downto 0) );
end entity gates;
-- Architecture
architecture RTL of gates is
begin
W <= A and B; U <= A nor B; --AND, NOR
X <= C xor D; Y <= C xnor D; --XOR, XNOR
Z <= (A and B) or (C and D); --AND-OR
vX <= vA and vB; -- Vector bitwise AND
vY <= vA or vB; -- Vector bitwise OR
end architecture RTL;
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Procedural logic version of a combinatorial logic circuit
-- Entity
entity gates is port (
A,B,C,D : in std_logic;
Y : out std_logic );
end entity gates;
-- Architecture
architecture combo of gates is
begin combo_process : process (A,B,C,D)
begin
if ((C='1') and (D='1')) then Y <= '0';
elsif ((A='1') or (B='1')) then Y <= '1';
else Y <= '0';
end if;
end process combo_process;
end architecture combo;
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Example D Latch (sets output q to d if gate is high.)
-- Entity
entity DLatches is port (
d, gate, clr : in std_logic;
q : out std_logic );
end entity DLatches;
-- Architecture
architecture LArch of DLatches is begin
latch_proc_1 : process (gate, d)
begin
if (gate='1') then q <= d;
-- No rising_edge()
end if;
-- No gate=0 value, so latch inferred
end process latch_proc_1;
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Combinatorial logic takes a finite time best/worst case to proagate a result through wires/logic cells in a chip. We can use
latches/D Flip flops to synchronize this logic. D FF's are similar to lateches, they just have a clk. Can use
rising_edge(signal) in an
if statement to get a rising edge of a value.
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Can use data registers to store data for later use. Here's an example in VHDL.
-- Entity
entity Data_Reg is port (
clk, reset, load : in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end entity Data_Reg;
-- Architecture
architecture Reg_Arch of Data_Reg is
begin dreg_proc : process (clk, reset, load)
begin
if (reset='0') then q <= "0000";
elsif (rising_edge(clk)) then
if (load='1') then q <= d;
end if;
end if;
end process dreg_proc;
end architecture Reg_Arch;
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Make sure to use newer VHDL (2008+) to be able to overload operators!
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Memories are a common element in most digital elements. Can extend a register to create a RAM/ROM.
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Can use multiple of a structure within an architecture to create a larger architecture. See below:
architecture Add16_Arch of Add16 is
component Add4 port (
A,B : in std_logic_vector(3 downto 0);
Cin : in std_logic; Cout : out std_logic);
Sum : in std_logic_vector(3 downto 0) );
end component;
Begin
Add4_u1 : Add4 port_map (
A=> A(3 downto 0), B=>(3 downto 0), Z=> Cin(0), Sum(3 downto 0) );
...
Add4_u4 : Add4 port_map (
A=> A(15 downto 12), B=>(15 downto 12), Z=> Cin(3), Sum(15 downto 12) );
end architecture Add16_Arch;
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Can use while/for the same way as in C in VHDL. See below for a while loop:
architecture Loop_Arch of my_loop is begin
while (I <= 8) loop
if (B = '1') then
Z(I) <= A(I);
end if;
I := I + 1;
end loop;
end architecture Loop_Arch;